Paul McKenney's paper on why memory barriers exist at all, built from the hardware up. It starts with how a CPU cache is laid out, then how the MESI protocol keeps caches agreeing on the value of each location, then how store buffers and invalidate queues quietly break that agreement in exchange for speed. Once you see those two queues, read and write barriers stop looking arbitrary and start looking like the obvious fix.
Ulrich Drepper's long guide from 2007 on how memory hardware really works and why memory, not the CPU, is often what makes a program slow. It covers how RAM chips work, how CPU caches are built and why they exist, and how virtual memory and NUMA change the picture, then spends a large middle section on concrete advice for writing code that uses caches well. There are plenty of diagrams and real numbers measured on real hardware, along with practical topics like data layout, cache line size, and tools that help you find memory related slowdowns. Some of the hardware details have aged, but the core ideas still hold up.